SDA55XX Datasheet, PDF (119/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
UART
11.2
Multiprocessor Communication
Modes 2 and 3 of the serial interface of the controller have a special provision for
multiprocessor communication. In these modes, 9 data bits are received. The 9th one
goes into RB8. Then comes a stop bit. The port can be programmed such that when the
stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature
is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor
communications is as follows.
When the master processor wants to transmit a block of data to one of the several
slaves, it first sends out an address byte which identifies the target slave. An address
byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte.
With SM2 = 1, no slave will be interrupted by a data byte. An address byte however, will
interrupt all slaves, so that each slave can examine the received byte and see if it is being
addressed. The addressed slave will clear its SM2 bit and prepare to receive the data
bytes that will be coming. The slaves that weren’t addressed leave their SM2s set and
go on about their business, ignoring the coming data bytes.
SM2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop
bit. In a mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a
valid stop bit is received.
Semiconductor Group
119
User’s Manual July 99