SDA55XX Datasheet, PDF (94/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Interrupts
Note: Active interrupts are only stored for one machine cycle. As a result, if an interrupt
was active for one or more polling cycles but not serviced for one of the reasons
given above, the interrupt will not be serviced.
For all other interupts interrupt request is stored as an interrupt flag in CISR0 and CISR1.
These request bits must be cleared by software while servicing the interrupt. These
interrupts always gets serviced once raised regardless of number of polling cycles
required to service them.
The rest of the functionality with regards to sampling from controller and requirements to
start the service are same as discussed above.
7.10
Interrupt Latency
The response time in a single interrupt system is between 3 and 9 machine cycles.
7.11
Interrupt Flag Clear .
In case of external interrupt 0 and external interrupt 1, If the external interrupts are edge
triggered, the interrupt flag is cleared on vectoring to the service routine but if they are
level triggered, the flag is controlled by the external signal. Timer/counter flags are
cleared on vectoring to the interrupt service routine. All other interrupt flag, including
external extra interrupt 0 and 1 are not cleared by hardware. They must be cleared by
software.
7.12
Interrupt return
For the proper operation of the interrupt controller. It is necessary that all interrupt
routines end with a RETI instruction.
7.13
Interrupt Nesting
The process whereby a higher-level interrupt request interrupts a lower-level interrupt
service program is called nesting. In this case the address of the next instruction in the
lower-priority service program is pushed onto the stack, the stack pointer is incremented
by two and processor control is transferred to the program memory location of the first
instruction of the higher-level service program. The last instruction of the higher-priority
interrupt service program must be a RETI-instruction. This instruction clears the higher
‘priority-level-active’ flip-flop. RETI also returns processor control to the next instruction
of the lower-level interrupt service program. Since the lower ‘priority-level-active’ flip-flop
Semiconductor Group
94
User’s Manual July 99