SDA55XX Datasheet, PDF (134/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
14.4
Functional description
Pulse Width Modulation Unit
14.4.1 8 bit PWM
The base frequency of a 8 bit resolution channel is derived from the overflow of a six bit
counter.
On every counter overflow, the enabled PWM lines would be set to 1. Execpt in the case
when compare value is set to zero.
In case the comparator bits (7...2) are set to 1, the high time of the base cycle is 63 clock
cycles. In case all the comparator bits (7...0) including the stretching bits are set to 1, the
high time of the full cycle (4 base cycles ) is 255 clock cycles.
The corrosponding PWCOMP8x register determines the duty cycle of the channel. When
the counter value is equal to or greater than the compare value then the output channel
is set to zero. The duty cycle can be adjusted in steps of fpwm as mentioned in the table.
In order to achieve the same resolution as 8 bit counter, the high time is stretched
periodically by one clock cycle. Stretching cycle is determined based on the two least
significant bits in the corresponding PWCOMP8x register.
The relationship for streching cycle can be seen in the following table and the example
below.
3:&203;
%LW 
%LW 
&\FOH VWUHWFKHG


‘stretched‘
Cycle 0 Cycle 1 Cycle 2 Cycle 3
Semiconductor Group
134
User’s Manual July 99