SDA55XX Datasheet, PDF (59/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
6
Microcontroller
Microcontroller
6.1
Architecture
Every cpu machine cycle consists of 12 internal cpu clock period.
The CPU manipulates operands in two memory spaces: the program memory space,
and the data memory space. The program memory address space is provided to
accommodate relocatable code.
The data memory address space is divided into the 256-byte internal data RAM, XRAM
(extended data memory, accessible with MOVX instructions) and the 128-byte Special
Function Register (SFR) address spaces. Four register banks (each bank has eight
registers), 128 addressable bits, and the stack reside in the internal data RAM. The stack
depth is limited only by the available internal data RAM. Its location is determined by the
8-bit stack pointer. All registers except the program counter and the four 8-register banks
reside in the special function register address space. These memory mapped registers
include arithmetic registers, pointers, I/O-ports, registers for the interrupt system, timers,
pulse width modulator, capture control unit, watchdog timer, UART, display, acquisition
control etc. Many locations in the SFR address space are addressable as bits.
Note that reading from unused locations within data memory will yield undefined data.
Conditional branches are performed relative to the 16 bit program counter. The register-
indirect jump permits branching relative to a 16-bit base register with an offset provided
by an 8-bit index register. Sixteen-bit jumps and calls permit branching to any location in
the memory address space.
The processor has five methods for addressing source operands: register, direct,
register-indirect, immediate, and base register plus index register-indirect addressing.
The first three methods can be used for addressing destination operands. Most
instructions have a ‘destination, source’ field that specifies the data type, addressing
methods and operands involved. For operations other than moves, the destination
operand is also a source operand.
Registers in the four 8-register banks can be accessed through register, direct, or
register-indirect addressing; the lower 128 bytes of internal data RAM through direct or
register-indirect addressing, the upper 128 bytes of internal data RAM through register-
indirect addressing; and the special function registers through direct addressing. Look-
up tables resident in program memory can be accessed through base register plus index
register-indirect addressing.
Semiconductor Group
59
User’s Manual July 99