SDA55XX Datasheet, PDF (101/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Power Saving modes
3//BUVW
3//6
3// UHVHW
0: PLL not reset
1: PLL reset
PLL reset sequence requires that PLL_rst = 1 for 10 micro second
then PLL_rst = 0, after that 150 microsecond are required till PLL is
locked.
3// 6OHHS
0: Power save Mode not started
1: Power save Mode started
Before the PLL is switched to power save mode (PLLS = 1), the SW
has to switch the clock source from 200 Mhz PLL clock to the 6
MHZ oscillator clock (CLK_Src = 1).
To switch back to the normal mode, software has to end the PLL
power save mode(PLLS=0), reset the PLL for 10 micro second ( 3
machine cycles), PLL_rst = 1 the back to 0, wait for 150 micro
seconds (38 machine cycles) and then switch back to the PLL
clock.
Semiconductor Group
101
User’s Manual July 99