SDA55XX Datasheet, PDF (153/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
17
Sync System
Sync System
17.1
General Description
The display sync system is completely independent from the acquisition sync
system (CVBS timing) and can either work as a sync master or as a sync slave
system. Talking about ’H/V-Syncs’ in this chapter and in chapter display
generator always refers to display related H/V Syncs and never to CVBS related
sync timing.
In sync slave mode TVTpro receives the synchronisation information from two
independent pins which deliver separate horizontal and vertical signals or a
sandcastle impulse from which the horizontal and vertical sync signals are
seperated internally. Due to the not line locked pixel clock generation (refer to
chapter ’Clock Processing’) it can process any possible horizontal and vertical
sync frequency.
In sync master mode of TVTpro delivers separate horizontal and vertical signals
with the same flexibility in the programming of there periods as in sync slave
mode.
17.1.1 Screen Resolution.
The number of displayable pixels on the screen is defined by the pixel
frequency (which is independent from horizontal frequency), the line period and
number of lines within a field. The screen is divided in three different regions:
Semiconductor Group
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User’s Manual July 99