SDA55XX Datasheet, PDF (212/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Display
18.6.5 Overview on the SFR registers
Next to the settings in the XRAM, SFR registers are used for OSD control:
SFR
address
F8h
name
bit
programma width
ble
purpose
EN_LD_GDW
yes
1 bit Used to avoid the download of the parameter settings
of the GDW from the RAM to the local display gene-
rator register bank. See also 18.4.2:
0: Download disabled
1: Download enabled
Initial value: 0
F8h
EN_DG_OUT
yes
1 bit Used to disable/enable the output of the display
generator.
If display generator is disabled the RGB outputs of
the IC are set to black and the outputs BLANK and
COR are set to.
COR = ENABLECOR
BLANK = ENABLEBLA
If display generator is enabled the display information
RGB, COR and BLANK is generated according to the
parameter settings in the XRAM.
0: Display generator is disabled
1: Display generator is enabled
F8h
DIS_COR
Initial value: 0
no
1 bit Defines the level of the COR output if display genera-
tor is disabled.
F8h
DIS_BLA
Initial value: 0
no
1 bit Defines the level of the BLANK output if display
generator is disabled.
F3h
POINTARRAY
no
1_1
F4h
POINTARRAY
no
1_0
F5h
POINTARRAY
no
0_1
F6h
POINTARRAY
no
0_0
Initial value: 1
6 bit Defines a pointer to a pointer array.
See also 18.6
Initial value: 0
8 bit Defines a pointer to a pointer array.
See also 18.6
Initial value: 0
6 bit Defines a pointer to a pointer array.
See also 18.6
Initial value: 0
8 bit Defines a pointer to a pointer array.
See also 18.6
Initial value: 0
Semiconductor Group
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User’s Manual July 99