SDA55XX Datasheet, PDF (88/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Default after reset: 00_H
(MSB)
&,65 ELW DGGUHVVHEOH
L24
ADC WTmr AVS
DVS PWtmr
Interrupts
SFR Address C0_H
(LSB)
AHS
DHS
L24
ADC
WTmr
AVS
DVS
PWtmr
AHS
1: Line 24 start interrupt occured, source bit set by hardware,
Source bit must be reset by software after servicing the interupt.
0:Interrupt has not occurred.
1: Analog to digital conversion complete source bit set by hardware
Source bit must be reset by software after servicing the interupt.
0:Interrupt has not occurred.
1: Watchdog in timer mode overflow source bit set by hardware
Source bit must be reset by software after servicing the interupt.
0:Interrupt has not occurred.
On reset this bit is intialized to 0, however if timer mode is selected
and timer is running, every over flow of timer will set this
bit.Therefore software must clear this bit before enabling the
corresponding interrupt.
1: Acquisition vertical sync interrupt source bit set by hardware
Source bit must be reset by software after servicing the interupt.
0:Interrupt has not occurred.
1: Display Vertical sync interrupt source bit set by hardware
Source bit must be reset by software after servicing the interupt.
0:Interrupt has not occurred.
1: PWM in timer mode overflow interrupt source bit set by hardware
Source bit must be reset by software after servicing the interupt.
0:Interrupt has not occurred.
On reset this bit is intialized to 0,however if timer mode is selected
and timer is running, every over flow of timer will set this bit.
Therefore software must clear this bit before enabling the
corresponding interrupt.
1: Acquisition horizental sync interrupt source bit set by hardware
Source bit must be reset by software after servicing the interupt.
0:Interrupt has not occurred.
Semiconductor Group
88
User’s Manual July 99