SDA55XX Datasheet, PDF (163/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Sync System
Bit
VSU2(3...0)
Function
Vertical Set Up Time 2 (Slave mode only)
To realize the odd/even detection of a field next to VSU a second
vertical setup time VSU2 is defined by the VSU2 register bits. This
horizontal delay is used to recognize the Vsync to another time than it
is recognized at VSU. The field detection is realized by detecting if in
between these two latching-points the VSync is rising or stable:
t_{V_delay2} = 3.84 us * VSU2
If VSYNC became active for both VSU and VSU2, an odd field is
detected. If VSYNC became active only for VSU an even field is
detected:
H
................
V
................
VSU2 VSU
VSU2
Generated field signal bei utilization of VSU and VSU2
field
VSU
with inverted VSU and VSU2:
H
................
V
................
VSU VSU2 VSU VSU2
VSU
Generated field signal bei utilization of VSU and VSU2
field
................
VSU2
Semiconductor Group
163
User’s Manual July 99