SDA55XX Datasheet, PDF (122/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
General Purpose Timers/Counters
– Mode 2
Mode 2 configures the timer/counter 0 register as an 8-bit counter (TL0) with automatic
reload, as shown in figure 12.1.3. Overflow from TL0 not only sets TF0, but also reloads
TL0 with the contents of TH0, which is preset by software. The reload leaves TH0
unchanged.
– Mode 3
Timer/counter 0 in mode 3 establishes TL0 and TH0 as two separate counters. TL0 uses
the timer 0 control bits: C/T, GATE, TR0, INT0 and TF0. TH0 is locked into a timer
function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1.
Thus, TH0 now controls the ‘timer 1’ interrupt.
Mode 3 is provided for applications requiring an extra 8-bit timer or counter. With timer 0
in mode 3, the processor can operate as if it has three timers/counters. When timer 0 is
in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3,
or can still be used in any application not requiring an interrupt.
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Timer/counter 1 can also be configured in one of four modes, which are selected by its
own bitpairs (M1, M0) in TMOD-register.
The serial port receives a pulse each time that timer/counter 1 overflows. This pulse rate
is divided to generate the transmission rate of the serial port.
Modes 0 and 1 are the same as for counter 0.
– Mode 2
The ‘reload’ mode is reserved to determine the frequency of the serial clock signal (not
implemented).
– Mode 3
When counter 1's mode is reprogrammed to mode 3 (from mode 0, 1 or 2), it disables
the increment counter. This mode is provided as an alternative to using the TR1 bit (in
TCON-register) to start and stop timer/counter 1.
12.1.2 Configuring the Timer/Counter Input
The use of the timer/counter is determined by two 8-bit registers, TMOD (timer mode)
and TCON (timer control). The input to the counter circuitry is from an external reference
(for use as a counter), or from the on-chip oscillator (for use as a timer), depending on
whether TMOD's C/T-bit is set or cleared, respectively. When used as a time base, the
on-chip oscillator frequency is divided by twelve or six before being used as the counter
input. When TMOD's GATE bit is set (1), the external reference input (T1, T0) or the
oscillator input is gated to the counter conditional upon a second external input (INT0),
(INT1) being high. When the GATE bit is zero (0), the external reference, or oscillator
input, is unconditionally enabled. In either case, the normal interrupt function of INT0 and
Semiconductor Group
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User’s Manual July 99