SDA55XX Datasheet, PDF (139/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Pulse Width Modulation Unit
Default after reset: 00_H
(MSB)
3:&203(;7< 
SFR-Address CA_H,CB_H
(LSB)
PCX14Y_7 PCX14Y_6 PCX14Y_5 PCX14Y_4 PCX14Y_3 PCX14Y_2 PCX14Y_1 PCX14Y_0
%LW 
%LW 
%LW 
%LW 
%LW 
%LW 
%LW 
PWM_direct
If this bit is set, every second PWM-Cycle is stretched by one
internal clock.
If this bit is set, every fourth PWM-Cycle is stretched by one internal
clock.
If this bit is set, every eighth PWM-Cycle is stretched by one internal
clock.
If this bit is set, every 16th PWM-Cycle is stretched by one internal
clock.
If this bit is set, every 32th PWM-Cycle is stretched by one internal
clock.
If this bit is set, every 64th PWM-Cycle is stretched by one internal
clock.
PWCOMEXT14_1 this bit is reseved for future use.
PWCOMEXT14_0, PWM_direct: If set, the counting rate of the
PWM (and the timer) is direct the incoming clock (33.33 MHz or
8.33 MHz in Slow-Down-Mode), then the Bit PWM_PR is ignored.
This bit effects all PWM channels and the timer-mode.
%LW 
PWM_PR
PWCOMEXT14_1 this bit is reseved for future use.
PWCOMEXT14_0,PWM_PR when this bit is set input counting
frequency is divided by 2 (PR bit).
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Semiconductor Group
139
User’s Manual July 99