SDA55XX Datasheet, PDF (83/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
7
Interrupts
Interrupts
7.1
Interrupt System
External events and the real-time on-chip peripherals require CPU service
asynchronous to the execution of any particular section of code. To couple the
asynchronous activities of these functions to normal program execution, a sophisticated
multiple-source, four-priority-level, nested interrupt system is provided.
7.2
Interrupt Sources
The TVT processor is capable of handling upto 24 interrupt sources. In SDA55xx 17
interrupts are implemented rest are reserved for future use. Processor acknowledges
interrupt requests from 17 sources. Two external sources via the INT0 and INT1 pins and
two additional external interrupts INTX0 and INTX1 are provided. Peripherals also use
interrupts. One from each of the two internal counters, one from the analog digital
converter and one from UART. In addition there are four Acquisition related interrupts,
two display related interrupts and one interrupt indicating change of channel, two
interrupts are generated by WDT and PWM overflow in timer mode.
Timer 0 and Timer 1 interrupts are generated byTCON.TF0 and TCON.TF1 following a
rollover in their respective registers (except in Mode 3 when TCON.TH0 controls the
Timer 1 interrupt).
The external interrupts INT0 and INT1 are either level or edge triggered depending on
bits in TCON and IRCON. Other external interrupts are level sensitive and active high.
Any edge triggering will need to be taken care of by individual peripherals.
INTX0 and INTX1 can be programed to be either negative or positive edge trigerred.
The analog digital converter interrupt is generated on completion of the analog digital
conversion.
Semiconductor Group
83
User’s Manual July 99