SDA55XX Datasheet, PDF (35/230 Pages) Infineon Technologies AG – Preliminary & Confidential

Preliminary & Confidential
4.2
Register Description
Default after reset: 01_H
(MSB)
3&/.
SDA 55xx
Clock System
PF(10)
SFR-Address DA
(LSB)
PF(9)
PF(8)
PF(10..8):
Qv‘ryÃA…r„ˆrp’ Ãshp‡‚…ÃHT7†
for detailed information refer to PCLK0
Default after reset: 48_H
(MSB)
PF(7)
PF(6)
PF(5)
3&/.
PF(4)
PF(3)
PF(2)
SFR-Address DB
(LSB)
PF(1)
PF(0)
PF(7..0):
Qv‘ryÃA…r„ˆrp’ Ãshp‡‚…ÃGT7†
This register defines the relation between the output pixel
frequency and the frequency of the crystal. The pixel frequency
does not depend on the line frequency. It can be calculated by the
following formula:
f_pixel = PF * 300MHz / 8192
The pixel frequency can be adjusted in steps of 36,6 KHz.
After power-on this register is set to 328_D. So, the default pixel
frequency is set to 12.01 MHz.
Attention: Register values greater then 874 generate pixel
frequencies which are outside of the specified boundaries.
Semiconductor Group
35
User’s Manual July 99