SDA55XX Datasheet, PDF (95/230 Pages) Infineon Technologies AG – Preliminary & Confidential

SDA 55xx
Preliminary & Confidential
Interrupts
has remained set, higher priority interrupts are re-enabled while further lower-priority
interrupts remain disabled.
7.14
External Interrupts
The external interrupt request inputs (NINT0 and NINT1) can be programmed for either
transition- activated or level-activated operation. Control of the external interrupts is
provided in the TCON register.
Default after reset: 00_H
(MSB)
7&21
SFR Address 88_H
(LSB)
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
IE1
IT1
IE0
IT0
TCON.7-4
Interrupt 1 edge flag. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed.
Interrupt 1 type control bit. Set/cleared by software to specify falling
edge/low level triggered external interrupts. IT1 = 1 selects
transition-activated external interrupts.
Interrupt 0 edge flag. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed.
Interrupt 0 type control bit. Set/cleared by software to specify falling
edge/low level triggered external interrupts. IT0 = 1 selects
transition-activated external interrupts.
See chapter ‘General Purpose Timers/Counters’
7.15
Extension of Standard 8051 Interrupt Logic
For more flexibility, the SDA545x family provides a new feature in detection EX0 and
EX1 in edge-triggered mode. Now there is the possibility to trigger an interrupt on the
falling and / or rising edge at the dedicated Port3-Pin. In order to use this feature
respective IT0 and IT1 bits in the TCON register must be set to activate edge triggering
mode. Table below shows combination for Interupt 0,however description is
trueforinterupt 1 also.
,7 (;5 (;)


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Semiconductor Group
95
User’s Manual July 99