PXB4330 Datasheet, PDF (95/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
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Register 12 TCT0
TCT Transfer Register 0
Register Descriptions
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
TCT0
32_H
Written and Read by CPU to maintain the TCT table;
the meaning of register TCT0 depends on the bit-field
’DWordSel’ in WAR;
Register WAR.DwordSel(1:0) = ’00’:
Bit
15
14
13
12
11
10
9
8
BufNrtMax(7:0)
Bit
7
6
5
4
3
2
1
0
BufNrtEPD(7:0)
BufNrtMax(7:0)
Maximum Buffer Fill Threshold for a non-real-time traffic class
configuration (register TCT1, DwordSel=00, RTind=0).
The first cell exceeding this threshold is discarded and if also PPD
is enabled for this traffic class (register TCT1, DwordSel=00,
PPDen=1) PPD is applied on a per connection (LCI) basis.
The threshold is defined with a granularity of 256 cells:
Threshold = BufNrtMax(7:0) * 256 Cells
BufNrtEPD(7:0)
EPD threshold for a non-real-time traffic class configuration
(register TCT1, DwordSel=’00’, RTind=0).
If the buffer fill exceeds this threshold and EPD is enabled for this
traffic class (register TCT1, DwordSel=00, EPDen=1) EPD is
applied on a per connection (LCI) basis.
The threshold is defined with a granularity of 256 cells:
Threshold = BufNrtEPD(7:0) * 256 Cells
Data Sheet
6-95
09.99