PXB4330 Datasheet, PDF (73/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Interface Descriptions
5.5
Clock Supply
The ABM Core is operated with a main chip clock, SYSCLK, with a frequency between
25 MHz and 52 MHz, as shown in Figure 5-8. The UTOPIA Interfaces have different
clocks: one for the PHY side interfaces (towards the PHY side in Figure 5-8), and one
for the ATM side interfaces (towards the ATM side in Figure 5-8). Both UTOPIA clocks
may be independent (asynchronous) to each other and also asynchronous to the System
Clock. The only restriction is that their frequency must be less than or equal to the Sys-
tem Clock.
J
2M SSDRAM
common
cell pointer
SYSCLK
Utopia PHY-Clock
161M6MSDSRDARMAM
upstream
cell storage
SYSCLK
SYSCLK
Utopia ATM-Clock
ALP
AOP
ABM
ASP
SYSCLK
161M6MSDSRDARMAM
downstream
cell storage
Figure 5-8 Clock Concept
A further asynchronous interface is the Microprocessor Interface. Its speed is limited to
less or equal than SYSCLK/2.
Note: The clock cycle for all RAMs is supplied by SYSCLK.
Data Sheet
5-73
09.99