PXB4330 Datasheet, PDF (163/201 Pages) Infineon Technologies AG – ICs for Communications

INITRAM
SDRAM
CORE
WGS
BIN
EFCI
Data Sheet
PXB 4330
Register Descriptions
Start of Initialization of the internal RAMs.
This bit is automatically cleared after execution.
1
Starts internal RAMs initialization procedure.
Note: The internal RAM initialization process can be
activated only once after hardware reset.
(0)
self-clearing
Initialization and configuration of the external SDRAMs. This bit
must be set to 1 after reset (initial pause of at least 200 µs is
necessary) and is automatically cleared by the ABM after
configuration of the SDRAMs has been executed.
1
Starts SDRAM initialization procedure
(0)
self-clearing
This bit disables the downstream ABM Core, which is necessary in
some MiniSwitch configurations (Uni-Directional Mode using one
core).
It is recommended to set CORE = 0 in Bi-directional operation
modes.
1
Downstream ABM core disabled
0
Downstream ABM core enabled
Selects MiniSwitch (Uni-directional) Mode if set to 1.
1
MiniSwitch (Uni-directional) operation mode selected:
upstream transmit UTOPIA interface is disabled;
downstream receive UTOPIA interface is disabled.
0
Normal (Bi-directional) operation mode
Indicate the usage of the CI/NI mechanism for ABR connections:
1
Enables CI/NI feedback
0
CI/NI feedback disabled
Indicate the usage of the EFCI mechanism for ABR connections:
1
Enables EFCI feedback
0
EFCI feedback disabled
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