PXB4330 Datasheet, PDF (112/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register 21 MASK2/MASK3
Table Access Mask Registers 2/3
Register Descriptions
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
MASK2
3D_H
MASK3
3E_H
Written by CPU to control internal table Read/Write
access
Bit
15
14
13
12
11
10
9
8
MASK(15:8)
Bit
7
6
5
4
3
2
1
0
MASK(7:0)
MASK2(15:0) Mask Register 2
MASK3(15:0) Mask Register 3
Mask Registers 0..3 control the Read-Modify-Write access from the
respective transfer registers to the internal tables on a per-bit
selection basis. The Mask Registers correspond to the respective
transfer registers (LCI0/LCI1, TCT0/TCT1, QCT0..3, SOT0/SOT1):
0
The dedicated bit of the transfer register is not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
1
The dedicated bit of the transfer register is overwritten
by the corresponding table entry bit during Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
Note: Registers MASK2 and MASK3 are only involved when accessing the Queue
Control Table (QCT). Due to the fact that only Read access is recommended for
this part of the QCT entries (see Queue Configuration Table Transfer Registers
QCT0..3), MASK2 and MASK3 should be programmed to FFFF_H during
initialization and should not be changed during operation.
Data Sheet
6-112
09.99