PXB4330 Datasheet, PDF (84/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Register 5 UBMTH/DBMTH
Upstream/Downstream Buffer Maximum Threshold Registers
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
UBMTH
24_H
Written by CPU
DBMTH
25_H
Bit
15
14
13
12
11
10
9
8
UBMTH/DBMTH(15:8)
Bit
7
6
5
4
3
2
1
0
UBMTH/DBMTH(7:0)
UBMTH(15:0)
DBMTH(15:0)
Upstream Buffer Maximum Threshold
Downstream Buffer Maximum Threshold
These bit fields determine a threshold for the total upstream and
downstream buffer size. The values depend on:
• The size of the external cell pointer RAM,
• Whether the downstream cell storage RAM is connected.
See Table 6-2 for recommended values.
Table 6-2 UBMTH/DBMTH Threshold Values
Cell Pointer RAM Downstream Cell RAM UBMTH
128 k x 16 bit
64 k x 16 bit
32 k x 16 bit
64 k x 16 bit
32 k x 16 bit
16 k x 16 bit
1 M x 32 bit
1 M x 32 bit
1 M x 32 bit
none
none
none
FFFF_H
7FFF_H
3FFF_H
FFFF_H
7FFF_H
3FFF_H
DBMTH
FFFF_H
7FFF_H
3FFF_H
0000_H
0000_H
0000_H
Note: An upstream cell storage RAM of size 1 M x 32 bit must be connected always.
Data Sheet
6-84
09.99