PXB4330 Datasheet, PDF (187/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Electrical Characteristics
Table 7-11 Transmit Timing (16-Bit Data Bus, 50 MHz at Cell Interface,
Multi-PHY)
No. Signal Name DIR Description
Limit Values
Min
Max
86 TXCLAV
A<P Input setup to TxClk
4
-
87
Input hold from TxClk
1
-
88
Signal going low impedance to 4
-
TxCLK
89
Signal going high impedance 0
-
to TxCLK
90
Signal going low impedance 1
-
from TxCLK
91
Signal going high impedance 1
-
from TxCLK
Unit
ns
ns
ns
ns
ns
ns
Table 7-12 Receive Timing (16-Bit Data Bus, 50 MHz at Cell Interface,
Multi-PHY)
No. Signal Name DIR Description
Limit Values
Min
Max
80 RXCLK
A>P RxClk frequency (nominal) 0
52
81
RxClk duty cycle
40
60
82
RxClk peak-to-peak jitter
-
5
83
RxClk rise/fall time
-
2
84 RXENB,
A>P Input setup to RxClk
4
-
85 ^RXADR[4:0]
Input hold from RxClk
1
-
Unit
MHz
%
%
ns
ns
ns
Data Sheet
7-187
09.99