PXB4330 Datasheet, PDF (146/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Register 43 SCEN0U/SCEN0D
Upstream/Downstream Scheduler Enable 0 Registers
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
SCEN0U 98_H
SCEN0D B8_H
Written by CPU for global Scheduler configuration
Bit
15
14
13
12
11
10
9
8
SchedEn(15:8)
Bit
7
6
5
4
3
2
1
0
SchedEn(7:0)
SchedEn(15:0)
Scheduler Enable
Each bit position enables/disables the respective Scheduler (15..0):
1
Scheduler enabled
0
Scheduler disabled
Data Sheet
6-146
09.99