PXB4330 Datasheet, PDF (126/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Register 32 QPTLU0/QPTLD0
QPT Upstream/Downstream Low Word Transfer Register 0
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
QPTLU0 60_H
QPTLD0 80_H
Written by CPU during queue initialization
Bit
15
14
13
12
11
10
9
8
Reserved(13:6)
Bit
7
6
5
4
3
2
1
0
Reserved(5:0)
flags(1:0)
Reserved(13:0)
These bits are used by the device logic. Do not Write to this field as
that could lead to complete malfunctioning of the ABM which can be
corrected by chip reset only.
flags(1:0)
These bits must be written to 0 when initializing the queue. Do not
Write during normal operation.
Data Sheet
6-126
09.99