PXB4330 Datasheet, PDF (68/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Interface Descriptions
5.2
RAM Interfaces
The ABM chip uses external, synchronous, dynamic RAM (SDRAM) for the storage of
ATM cells and external, synchronous, static RAM (SSRAM) for the storage of cell point-
ers. Two SDRAM Interfaces and one SSRAM Interface are provided. Each of the two
SDRAM Interfaces is associated with one of the ABM Cores. The SSRAM Interface is
shared by both ABM Cores. All RAM Interfaces are operated with the system clock of up
to 52 MHz.
The size of the SDRAMs is fixed to 32 Mbit per ABM Core; but, the size of the SSRAM
depends on the required cell store size:
Table 5-4 External RAMs
Cell Store Size
Upstream
Downstream
64K cells
64K cells
32K cells
32K cells
16K cells
16K cells
64K cells
0
32K cells
0
16K cells
0
SDRAM Size
Upstream
Downstream
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
32Mbit
none
32Mbit
none
32Mbit
none
SSRAM Size
Common
128K × 16bit
128K × 16bit
128K × 16bit
64K × 16bit
32K × 16bit
16K x 16bit
The following pipelined SSRAM types are possible:
1. 2M RAM 128K×16 bit,
for example: Micron MT58LC128K18 Pipelined or Samsung KM718V789/L
2. 4M RAM 128K×32/36 bit with only 16 data bits connected
3. 2M RAM 64K×32 bit,
for example, Toshiba TC55V2325 with only 16 data bits connected
4. 1M RAM 32K×32 bit with only 16 data bits connected
5. 1M RAM 64K×16 bit.
For the SDRAM, the Infineon 16 M type HYB39S16160AT-12 [6], IBM0316169C-13, or
equivalent are recommended. Devices faster than 13 ns (77 MHz) are usable as well.
Figure 5-3 shows an example of the maximum SSRAM size with 2 Mbit devices.
Data Sheet
5-68
09.99