PXB4330 Datasheet, PDF (124/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
•
Table 6-12 Registers for QPT Downstream Table Access
63
32
QPT RAM entry high word(Downstream)
RAM select:
15
0 15
0
15
0
QPTHD1
QPTHD0
MAR=19_H
Entry select:
15
0 15
0
15
0
QMSKD1
QMSKD0
WAR (0..1023_D)
31
0
QPT RAM entry low word (Downstream)
15
0 15
0
QPTLD1
QPTLD0
15
0 15
0
QMSKD1
QMSKD0
RAM select:
15
0
MAR=18_H
Entry select:
15
0
WAR (0..1023_D)
QPTHU1 and QPTHU0 are the transfer registers for the 32-bit high word of one
upstream QPT table entry. QPTLU1 and QPTLU0 are the transfer registers for the 32-bit
low word of one upstream QPT table entry. Access to high and low word are both
controlled by mask registers QMSKU1 and QMSKU0.
The register set for accessing the downstream QPT table entries is equal to the
upstream set.
The queue number representing the table entry which needs to be Read or modified
must be written to the Word Address Register (WAR). The dedicated QPT table entry is
Read into the QPTxy1/QPTxy0 registers (x=H,L; y=U,D) or modified by the QPTxy1/
QPTxy0 register values with a Read-Modify-Write mechanism. The associated mask
registers QMSKy0 and QMSKy1 allow a bit-by-bit selection between Read (1) and Write
(0) operation. In case of Read operation, the dedicated QPTxy1/QPTxy0 register bit will
be overwritten by the respective QPT table entry bit value. In case of Write operation, the
dedicated QPTxy1/QPTxy0 register bit will modify the respective QPT table entry bit
value.
Data Sheet
6-124
09.99