PXB4330 Datasheet, PDF (147/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Register 44 SCEN1U/SCEN1D
Upstream/Downstream Scheduler Enable 1 Registers
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
SCEN1U 99_H
SCEN1D B9_H
Written by CPU for global Scheduler configuration
Bit
15
14
13
12
11
10
9
8
SchedEn(31:24)
Bit
7
6
5
4
3
2
1
0
SchedEn(23:16)
SchedEn(31:16)
Scheduler Enable
Each bit position enables/disables the respective Scheduler
(31..16):
1
Scheduler enabled
0
Scheduler disabled
Data Sheet
6-147
09.99