PXB4330 Datasheet, PDF (75/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Table 6-1 ABM Registers Overview
Addr Register
(hex)
Description
Reset µP ^See
value
pag
e
(hex)
Cell Flow Test Registers
01/11 UCFTST/
DCFTST
Upstream/Downstream Cell Flow Test
Registers
0000 R/W 80
SDRAM Configuration Registers
02/12 URCFG/
DRCFG
Upstream/Downstream SDRAM
Configuration Registers
0033 R/W 82
Buffer Occupation Counter Registers
20
UBOC
21
DBOC
Upstream/Downstream Buffer
Occupation Registers
0000 R 82
0000 R 82
22
UNRTOC
23
DNRTOC
Upstream/Downstream Non-Real-Time 0000 R 83
Buffer Occupation Registers
0000 R 83
Buffer Threshold Registers
24
UBMTH
25
DBMTH
Upstream/Downstream Buffer Maximum 0000 R/W 84
Threshold Registers
0000 R/W 84
26
UCIT
27
DCIT
Upstream/Downstream ABR Congestion 0000 R/W 85
Indication Threshold Registers
0000 R/W 85
2C UEC
2D DEC
Upstream/Downstream EPD CLP1
Threshold Registers
0000 R/W 88
0000 R/W 88
Occupation Capture Registers
28
UMAC
29
DMAC
Upstream/Downstream Maximum
Occupation Capture Registers
0000 R 86
0000 R 86
2A UMIC
2B DMIC
Upstream/Downstream Minimum
Occupation Capture Registers
FFFF R 87
FFFF R 87
LCI Table Transfer Registers LCI0, LCI1
30
LCI0
LCI Transfer Register 0
0000 R/W 90
31
LCI1
LCI Transfer Register 1
0000 R/W 92
Traffic Class Table Transfer Registers TCT0, TCT1
32
TCT0
TCT Transfer Register 0
0000 R/W 95
33
TCT1
TCT Transfer Register 1
0000 R/W 98
Data Sheet
6-75
09.99