PXB4330 Datasheet, PDF (130/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Internal Table 6: Scheduler Configuration Table Fractional Transfer Registers
The Scheduler Configuration Table Fractional Transfer Registers are used to access the
internal Upstream/Downstream Scheduler Configuration Tables Fractional Part (SCTF)
containing 48 entries each. Table 6-14 and Table 6-15 summarize the registers.
Table 6-14 Registers SCTF Upstream Table Access
15
0
SCTF RAM Entry
(Upstream)
RAM Select:
15
0
15
0
SCTFU
MAR=17_H
Entry Select:
15
0
15
0
SMSKU
WAR (0..47_D)
Table 6-15 Registers SCTF Downstream Table Access
15
0
SCTF RAM Entry
(Downstream)
RAM Select:
15
0
15
0
SCTFD
MAR=1F_H
Entry Select:
15
0
15
0
SMSKD
WAR (0..47_D)
SCTFU and SCTFD are transfer registers for one 16-bit SCTF upstream/downstream
table entry. The upstream and downstream Schedulers use different tables (internal
RAMs) addressed via the MAR. The Scheduler number representing the table entry
which needs to be Read or modified must be written to the WAR (Word Address
Register). The dedicated SCTFU/D table entry is Read into the SCTFU/D registers or
modified by the SCTFU/D register value with a Read-Modify-Write mechanism. The
associated mask registers, SMSKU and SMSKD, allow a bit-by-bit selection between
Read (1) and Write (0) operation. In case of Read operation, the dedicated SCTFU/D
register bit will be overwritten by the respective SCTFU/D table entry bit value. In case
Data Sheet
6-130
09.99