PXB4330 Datasheet, PDF (186/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Electrical Characteristics
Table 7-10 Receive Timing (16-Bit Data Bus, 50 MHz at Cell Interface, Single
PHY)
No. Signal Name DIR Description
Limit Values Unit
Min
Max
80 RXCLK
A>P RxClk frequency (nominal) 0
52
MHz
81
RxClk duty cycle
40
60
%
82
RxClk peak-to-peak jitter
-
5
%
83
RxClk rise/fall time
-
2
ns
84 RXENB
A>P Input setup to RxClk
4
-
ns
85
Input hold from RxClk
1
-
ns
86 RXDAT[15:0], A<P Input setup to RxClk
4
-
ns
87 ^RXPTY,
RXSOC,
Input hold from RxClk
1
-
ns
RXCLAV
Table 7-11 Transmit Timing (16-Bit Data Bus, 50 MHz at Cell Interface,
Multi-PHY)
No. Signal Name DIR Description
Limit Values
Min
Max
80 TXCLK
A>P TxClk frequency (nominal) 0
52
81
TxClk duty cycle
40
60
82
TxClk peak-to-peak jitter
-
5
83
TxClk rise/fall time
-
2
84 TXDAT[15:0], A>P Input setup to TxClk
85 ^TXPTY,
TXSOC,
Input hold from TxClk
TXENB,
TXADR[4:0]
4
-
1
-
Unit
MHz
%
%
ns
ns
ns
Data Sheet
7-186
09.99