PXB4330 Datasheet, PDF (74/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
6
Register Descriptions
This chapter provides both an overview of the ATM Buffer Manager PXB 4330 Register
Set and detailed register descriptions and Table Access descriptions.
6.1
Overview of the ABM Register Set
Control and operation of the ABM chip can be done by directly configuring Status
Registers or, to a large extent, by programming the internal tables. Access to these
tables is not direct, but occurs via Transfer Registers and Transfer Commands. Any
transfer must be prepared by writing appropriate values to the Transfer Registers. Bit
positions named ’don’t Write’ must be masked by writing 1 to the corresponding bit
positions in the Mask Register. This avoids overwriting these table bit positions with the
Transfer Register contents, which would cause fatal malfunction. The specific table
position which should be modified with the Transfer Register contents is selected via
Register WAR. Transfer is started by writing the table address to Register MAR and also
setting the ’Start’ bit. The ABM device will reset the ’Start’ bit after transfer completion.
The ABM contains the following internal tables for configuration:
• LCI Table
• Traffic Class Table
• Queue Configuration Table
• Queue Parameter Table (consisting of 4 tables)
• Scheduler Block Occupancy Table
• Scheduler Rate Table (consisting of 4 tables)
The Status Registers and Transfer Registers are described below in Table 6-1. This
register overview table is organized by functional groups and, thus, not always in
sequence to the offset addresses. Offset addresses are 16-bit word addresses.
Addresses not listed in this table are either associated with Reserved Registers or are
unused. Performing Write accesses to those addresses is not recommended in order to
prevent malfunctions and to guarantee upwards compatibility to future versions of the
device.
Data Sheet
6-74
09.99