PXB4330 Datasheet, PDF (125/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
The Read-Modify-Write process is controlled by the Memory Address Register (MAR).
The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be
accessed; to select the QPT table bit field MAR(4:0) must be set to
11_H for QPT upstream table high word,
10_H for QPT upstream table low word,
19_H for QPT downstream table high word,
18_H for QPT downstream table low word.
Bit 5 of MAR starts the transfer and is cleared automatically after execution of the Read-
Modify-Write process.
Table 6-13 WAR Register Mapping for QPT Table Access
Bit
15
14
13
12
11
10
Unused(5:0)
9
8
QueueSel9:8)
Bit
7
6
5
4
3
2
1
0
QueueSel(7:0)
QueueSel(9:0) Selects one of the 1024 queue parameter table entries.
Data Sheet
6-125
09.99