PXB4330 Datasheet, PDF (93/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Internal Table 2: Traffic Class Table Transfer Registers TCT0, TCT1
The Traffic Class Table Transfer Registers are used to access the internal Traffic Class
Table (TCT) containing 2*16 entries of 128 bits each (16 traffic classes per ABM core).
Table 6-5 shows an overview of the registers involved.
Table 6-5 Registers for TCT Table Access
31
0
TCT RAM entry
15
0 15
0
TCT1
TCT0
15
0 15
0
MASK1
MASK0
RAM select:
15
0
MAR=01_H
TCT entry select:
15
0
WAR (0..127_D)
TCT0 and TCT1 are the transfer registers used to access the 128 bit TCT table entries.
Core selection, traffic class number, and 32-bit word selection of the table entry which
needs to be Read or Modified must be programmed to the Word Address Register
(WAR). The dedicated TCT table entry 32-bit word is Read into the TCT1/TCT0 registers
or Modified by the TCT1/TCT0 register values with a Read-Modify-Write mechanism.
The associated Mask Registers MASK0 and MASK1 allow a bit-by-bit selection between
Read (1) and Write (0) operations. In case of Read operation, the dedicated TCT1/TCT0
register bit will be overwritten by the respective TCT table entry bit value. In case of Write
operation, the dedicated TCT1/TCT0 register bit will modify the respective TCT table
entry bit value.
The Read-Modify-Write process is controlled by the Memory Address Register (MAR).
The 5 LSBs (= Bit 4..0) of the MAR select the memory/table that will be accessed; to
select the TCT table bit field MAR(4:0) must be set to 1. Bit 5 of MAR starts the transfer
and is automatically cleared after execution of the Read-Modify-Write process.
Table 6-6 WAR Register Mapping for TCT Table Access
Bit
15
14
13
12
11
10
9
8
Unused(7:0)
Bit
7
6
5
4
3
2
1
0
Unused CoreSel
TrafClass(3:0)
DwordSel(1:0)
Data Sheet
6-93
09.99