PXB4330 Datasheet, PDF (152/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register 47 ISRD
Interrupt Status Register Downstream
Register Descriptions
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
ISRD
D1_H
Read by CPU to evaluate interrupt events related to the
upstream core. Interrupt indications must be cleared by
writing a 1 to the respective bit locations; writing a 0 has
no effect;
Bit
15
14
13
12
11
10
9
8
Unused(1:0)
QIDINV BUFER LCI PARITY SOCER BUFER
1
INVAL ER
2
Bit
7
6
5
4
3
2
1
0
BUFER CDVOV MUXOV ^BUFER4/ RMCER BIP8ER BUFER VCRM
3
CNTUF
5
ER
QIDINV
This interrupt is generated if the ABM tries to Write a cell into a
disabled queue. The cell is discarded.
(Typically occurs on queue configuration errors.)
BUFER1
Unexpected Buffer Error number 1. Should never occur in normal
operation. Immediate reset of the chip is recommended.
LCIINVAL
Cell with invalid LCI received, i.e. a LCI value >8191. The cell is
discarded.
PARITYER
Parity Error at UTOPIA receive downstream (PHY) interface
detected.
SOCER
Start of Cell Error at UTOPIA receive downstream (PHY) interface
detected.
Data Sheet
6-152
09.99