PXB4330 Datasheet, PDF (30/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Pin Descriptions
Some pins are connected to an internal pull up resistor or to an internal pull down resis-
tor. Such pins are indicated as follows in Table 2-1:
• Pins shown with a ¹⁾ are connected with an internal pull up resistor.
• Pins shown with a ²⁾ are connected with an internal pull down resistor.
Note: The ABM signal pins are not 5V I/O tolerant. For further details refer to "Electrical
Characteristics" on page 7-174.
Table 2-1
Pin No.
Pin Definitions and Functions
Symbol
Input (I) Function
Output (O)
Clock and Reset (4 pins)
F24
G23
AB24
E1
RESET
I
SYSCLK I
UTPHYCLK I
UTATMCLK I
Chip Reset
Main Chip Clock
UTOPIA Clock at PHY side (Master).
UTOPIA Clock at ATM side (Slave).
Utopia Interface Receive Upstream Master (30 pins)
N23, M26,
M25, M24,
L26, M23,
L25, K26,
L24, K25,
L23, J26,
K24, J25,
H26, K23 ²⁾
G26, H24,
G25, F26
J24 ²⁾
H23, G24,
F25, E26
P24, P25,
N25, N24 ²⁾
H25 ²⁾
RXDATU I
(15:0)
RXADRU O
(3:0)
RXPRTYU I
RXENBU O
(3:0)
RXCLAVU I
(3:0)
RXSOCU I
Receive Data Bus from PHY side.
Address Outputs to PHY side.
Odd Parity of RXDATU(15:0) from PHY side.
Enable signal to PHY side.
Cell Available signal from PHY side.
Start of Cell signal from PHY side.
Data Sheet
2-30
09.99