PXB4330 Datasheet, PDF (168/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Register 57 UTATM0
UTOPIA Configuration Register 0 (ATM Side)
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
UTATM0 DF_H
Written and Read by CPU
Bit
15
14
13
12
11
10
9
8
Unused(11:4)
Bit
7
•
BUS
6
5
Unused(3:0)
4
3
2
1
0
BUS UTPAR UTCONFIG(1:0)
The UTOPIA interface can be used with 16 bit or 8 bit buswidth:
0
8-bit mode at ATM side.
1
16-bit mode at ATM side.
UTPAR
Enables the parity check at UTOPIA receive downstream interface:
0
Parity check disabled at ATM side
1
Parity check enabled at ATM side
UTCONFIG(1:0)
Configuration of port mode at ATM side UTOPIA interface:
00
4 x 6 port
01
3 x 8 port
10
2 x 12 port
11
Level 1 mode (4 x 1 port)
Data Sheet
6-168
09.99