PXB4330 Datasheet, PDF (135/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
SCTIU and SCTID are the transfer registers for the 32-bit SCTI upstream/downstream
table entries. The upstream and downstream Schedulers use different tables (internal
RAMs) addressed via dedicated registers, SADRU/SADRD. The address registers
select the scheduler-specific entry as well as the high or low word of a 32-bit entry to be
accessed. Further, there is no command bit, but transfers are triggered via Write access
of the address registers and the data registers:
• To initiate a Read access, the Scheduler number must be written to the address
register SADRU (upstream) or to the address register SADRD (downstream). One
system clock cycle later, the data can be Read from the respective transfer register
SCTIU or SCTID.
• To initiate a Write access, it is sufficient to Write the desired Scheduler number to the
address registers, SADRU and SADRD, and then Write the desired data to the
respective transfer register, SCTIU or SCTID, respectively. The transfer to the integer
table is executed one system clock cycle after the Write access to SCTIU or SCTID.
Thus, consecutive Write cycles may be executed by the microprocessor.
The SCTI table entries are either read or written. Thus, no additional mask registers are
provided for bit-wise control of table entry accesses.
Data Sheet
6-135
09.99