PXB4330 Datasheet, PDF (113/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register 22 CONFIG
Configuration Register
Register Descriptions
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
41_H
Written by CPU
Bit 15
14
13
12
11
10
9
8
Unused(13:6)
Bit
7
6
5
4
3
Unused(5:0)
2
1
0
Reserved1 ABRTQ
Reserved1
this bit is for internal use only and must be set at 0 during normal
operation.
ABRTQ
ABR Toggle Queue ID:
This global bit controls treatment of RM cells for uni-directional
(miniswitch) mode.
0
Normal Operation (set for bi-directional mode).
1
Only RM cells with toggled LCI and QID are modified.
Note: The following conditions must apply for proper CI/NI operation:
In Bi-directional Mode, the same LCI and the same queue identifier QID must be
used for the ABR connection in forward and backward directions; for example, in
forward direction LCI=2 and QID=7, in backward direction LCI=2 and QID=7.
In Uni-directional Mode, LCI and QID must have the LSB inverted; for example,
in forward direction LCI=3 and QID=7, in backward direction LCI=2 and QID=6.
The LCI inversion (toggle) is activated by setting the LCI toggle bit in the MODE
register to 1.
Data Sheet
6-113
09.99