PXB4330 Datasheet, PDF (190/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Electrical Characteristics
Table 7-13 SSRAM Interface AC Timing Characteristics (cont’d)
No. Parameter
Limit Values
Unit
Min
Typ
Max
105 Setup time RDATx Input before
5
ns
SYSCLK rising (read cycles)
106 Hold time RDATx Input after SYSCLK 3
ns
rising (read cycles)
7.4.5 SDRAM Interface
Timing of the Synchronous Dynamic RAM Interface is simplified as all signals are refer-
enced to the rising edge of SYSCLK. In Figure 7-9, it can be seen that all signals output
by the PXB 4330 E ABM have identical delay times with reference to the clock. When
reading from the RAM, the PXB 4330 E ABM samples the data within a window at the
rising clock edge.
SYSCLK
A(10:0), RAS,
CAS, CS, WE
DQ(31:0), output
DQ(31:0), input
110
111
112
113
114
115 116
Figure 7-9 Generic SDRAM Interface Timing Diagram
Table 7-14 SDRAM Interface AC Timing Characteristics
No. Parameter
Limit Values
Min
Typ
Max
110 T_SYSCLK : Period SYSCLK
19.3
110A F_SYSCLK : Frequency SYSCLK
52
Unit
ns
MHz
Data Sheet
7-190
09.99