PXB4330 Datasheet, PDF (109/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
LDSTH(7:0)
Level Detection Scheduler Threshold High.
If the upstream counter SchedOcc(15:0) (SOT1) equals or exceeds
this threshold, the corresponding indication bit for this Scheduler in
the registers LEVH0..LEVH2 is set to 1. The threshold is defined
with a granularity of 256:
Threshold = LDSTH(7:0) * 256 Cells
LDSTL(7:0)
Level Detection Scheduler Threshold Low.
If the upstream counter SchedOcc(15:0) (SOT1) equals or exceeds
this threshold, the corresponding indication bit for this Scheduler in
the registers LEVL0..LEVL2 is set to 1. The threshold is defined with
a granularity of 256:
Threshold = LDSTL(7:0) * 256 Cells
Note: As soon as the Scheduler fill level falls below a threshold, the corresponding
indication bit in registers LEVH0..2 or LEVL0..2 is cleared.
Note: Bit fields LDSTH and LDSTL are provided in the SOT table for the upstream and
downstream core as well. But, automatic level detection, by comparing these
values with the respective counters SchedOcc(15:0) and status indication in
registers LEVH0..2 and LEVL0..2, is supported for upstream Schedulers only.
Data Sheet
6-109
09.99