PXB4330 Datasheet, PDF (104/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register 15 QCT1
Queue Configuration Transfer Register 1
Register Descriptions
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
QCT1
35_H
Written and Read by CPU to maintain the LCI table
Bit
15
14
13
12
11
10
Unused QIDvalid
TrafClass(3:0)
9
8
SID(5:4)
Bit
7
6
5
SID(3:0)
4
3
2
1
0
ABRdir
flags(2:0)
QIDvalid
Queue Enable:
0
Queue disabled.
An attempt to store a cell to a disabled queue leads to a
discard of the cell and a QIDINV interrupt is generated.
If a filled queue gets disabled, cells may still be in the
queue and they will be Read out. Actual filling of the
queue can be obtained via QueueLength(13:0)
parameter in the QCT entry.
1
Queue enabled.
Cells are allowed to enter the queue.
TrafClass(3:0)
Traffic Class Number (0..15)
Assigns the queue to one of the 16 traffic classes defined in the
traffic class table TCT for this core.
SID(5:0)
Scheduler Number (0..47)
Assigns the queue to one of the 48 schedulers of this core.
ABRdir
ABR CI/NI update of backward RM cells:
0
RM cells of the same core are updated.
1
RM cells of the opposite core are updated.
Data Sheet
6-104
09.99