PXB4330 Datasheet, PDF (18/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Overview
• Per-VC queuing for VBR-nrt, ABR, UBR+, GFR
• Guaranteed rates, programmable per queue, via weight factors for VBR-nrt, ABR,
UBR+
• PCR limitation programmable for VBR-nrt, ABR, UBR
• EFCI marking and CI/NI update in backward RM cells for ABR
• Per connection optional EPD/PPD support for ABR, UBR and UBR+
• Selective low-priority packet discard for GFR
• Queue sharing for UBR
• Up to 16 traffic classes with individual thresholds
Thresholds
• Cell acceptance based on thresholds
• Thresholds for individual queues, traffic classes, schedulers and whole buffer
• PPD/maximum discard thresholds
• EPD discard thresholds
• CLP discard thresholds
• EFCI and CI/NI thresholds
Interfaces
• Two external SDRAM Interfaces for cell storage, one for upstream and one for
downstream direction, each 2 x 16 Mbit for 64K cells
• One common cell pointer SSRAM Interface with 128K x 16bit or 64K x 16bit
• Multiport UTOPIA Level 2 Interface in up- and downstream direction according to The
ATM Forum, UTOPIA Level 1 and 2 specifications [1, 2]
• 4-cell FIFO buffer at UTOPIA upstream interfaces and downstream receive interface
• 64-cell shared buffer for up to 24 PHYs at UTOPIA downstream transmit interface
• 16-bit Microprocessor Interface, configurable as Intel or Motorola type
• Boundary Scan Interface according to JTAG [4]
Supervision Functions
• Internal pointer supervision
• Cell header protection function
Technology
• 0.35 µ CMOS
• Ball Grid Array BGA-352 package (Power BGA)
• Temperature range from -40°C to 85°C
• Power dissipation 1.3 W (typical)
Data Sheet
1-18
09.99