PXB4330 Datasheet, PDF (149/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register 46 ISRU
Interrupt Status Register Upstream
Register Descriptions
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
ISRU
D0_H
Read by CPU to evaluate interrupt events related to the
upstream core. Interrupt indications must be cleared by writing
a 1 to the respective bit locations; writing a 0 has no effect;
Bit
15
14
13
12
11
10
9
8
Unused RAMER QIDINV BUFER LCI PARITY SOCER BUFER
1
INVAL ER
2
Bit
7
6
5
4
3
2
1
0
BUFER CDVOV MUXOV ^BUFER4/ RMCER BIP8ER BUFER VCRM
3
CNTUF
5
ER
RAMER
Configuration of common Cell Pointer RAM has been changed after
cells have been received (see Register MODE, bit field CPR).
(This is a global interrupt shared by both cores. That is, it is not
exclusively related to the Upstream Core.)
QIDINV
This interrupt is generated if the ABM tries to write a cell into a
disabled queue. The cell is discarded in this case.
(Typically occurs on queue configuration errors.)
BUFER1
Unexpected buffer error number 1. Should never occur in normal
operation. Immediate reset of the chip recommended.
LCIINVAL
Cell with invalid LCI received, that is, a LCI value > 8191.
The cell is discarded.
PARITYER
Parity error at UTOPIA receive upstream (PHY) Interface detected.
Data Sheet
6-149
09.99