PXB4330 Datasheet, PDF (116/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Register 25 LEVL2
Upstream Scheduler Lower Threshold Reached Indication Register 2
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read
0000_H
47_H
Read by CPU
Bit
15
14
13
12
11
10
9
8
SchedIndLow(47:40)
Bit
7
6
5
4
3
2
1
0
SchedIndLow(39:32)
SchedIndLow
(47:32)
These bits represent the respective upstream scheduler(47:32) and
indicate that its lower scheduler threshold configured in the SOT0
table is reached or exceeded; that is, more cells are currently stored
than specified by the LDSTL threshold value:
bit i=1 Scheduler i lower threshold reached or exceeded.
Data Sheet
6-116
09.99