PXB4330 Datasheet, PDF (88/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Register 9 UEC/DEC
Upstream/Downstream EPD CLP1 Threshold Registers
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
UEC
2C_H
Written by CPU
DEC
2D_H
Bit
15
14
13
12
11
10
9
8
UEC/DEC(15:8)
Bit
7
6
5
4
3
2
1
0
UEC/DEC(7:0)
UEC(15:0)
DEC(15:0)
Upstream EPD CLP1 Threshold value
Downstream EPD CLP1 Threshold value
These 16-bit values determine a global cell filling level threshold
that triggers explicit packet discard (EPD) for CLP=1 tagged frames
used by GFR traffic class service (low watermark).
Data Sheet
6-88
09.99