PXB4330 Datasheet, PDF (85/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Register 6
UCIT/DCIT
Upstream/Downstream ABR Congestion Indication Threshold
Registers
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
UCIT
26_H
Written by CPU
DCIT
27_H
Bit
15
14
13
12
11
10
9
8
UCIT/DCIT(15:8)
Bit
7
6
5
4
3
2
1
0
UCIT/DCIT(7:0)
UCIT(15:0)
DCIT(15:0)
Upstream ABR Congestion Indication Threshold
Downstream ABR Congestion Indication Threshold
These 16-bit counters determine a threshold for the total buffer fill
level with non-real-time cells to indicate ABR Congestion.
Congestion indication ’CI’ will be marked in cells belonging to ABR
traffic class if the number of stored non-real-time cells exceeds the
threshold value.
Data Sheet
6-85
09.99