PXB4330 Datasheet, PDF (137/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Register 39 SCTIU/SCTID
Upstream/Downstream SCTI Transfer Registers
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
SCTIU
91_H
SCTID
B1_H
Written by CPU to maintain the SCTI tables
Register SADRx.WSel = 0:
Bit
15
14
13
12
11
10
9
8
unused(1:0)
IntRate(13:8)
Bit
7
6
5
4
3
2
1
0
IntRate(7:0)
IntRate(13:0)
Integer Rate
This value determines the integer part of the Scheduler output rate.
Note: Recommendation for changing the UTOPIA port number or scheduler rate
during operation:
Disable specific scheduler by read-modify-write operation to corresponding bit in
registers SCEN0U/SCEN0D... SCEN2U/SCEN2D.
Modify scheduler specific UTOPIA port number and rates via Table 7 "Scheduler
Configuration Table Integer Transfer Registers" on page 6-134, registers SCTIU/
SCTID and Table 6 "Scheduler Configuration Table Fractional Transfer
Registers" on page 6-130, registers SCTFU/SCTFD.
Enable specific scheduler by read-modify-write operation to corresponding bit in
registers SCEN0U/SCEN0D... SCEN2U/SCEN2D.
Data Sheet
6-137
09.99