PXB4330 Datasheet, PDF (86/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Register 7 UMAC/DMAC
Upstream/Downstream Maximum Occupation Capture Registers
CPU Accessibility: Read only, self-clearing on Read
Reset Value:
Offset Address:
Typical Usage:
0000_H
UMAC
28_H
Read by CPU
DMAC
29_H
Bit
15
14
13
12
11
10
9
8
UMAC/DMAC(15:8)
Bit
7
6
5
4
3
2
1
0
UMAC/DMAC(7:0)
UMAC(15:0)
DMAC(15:0)
Upstream Maximum Occupation Capture Counter
Downstream Maximum Occupation Capture Counter
These 16-bit counters measure the absolute maximum number of
cells stored in the respective external cell buffer since the last Read
access (peak cell filling level within measurement interval). The
counter value is automatically cleared to 0000_H after Read.
Data Sheet
6-86
09.99