PXB4330 Datasheet, PDF (103/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Table 6-8 WAR Register Mapping for LCI Table Access
Bit
15
14
13
12
Unused(4:0)
11
10
CoreSel
9
8
QSel(9:8)
Bit
7
6
5
4
3
2
1
0
QSel(7:0)
CoreSel
Selects an ABM Core:
0
Upstream core selected
1
Downstream core selected
QSel(9:0)
Selects a Queue Entry within the range (0..1023).
Register 14 QCT0
Queue Configuration Transfer Register 0
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
QCT0
34_H
Read by CPU to maintain the QCT table
Bit
15
14
13
12
11
10
9
8
Unused(1:0)
QueueLength(13:8)
Bit
7
6
5
4
3
2
1
0
QueueLength(7:0)
QueueLength
(13:0)
Represents the Current Number of Cells Stored in this Queue.
Do not Write in normal operation.
Data Sheet
6-103
09.99