PXB4330 Datasheet, PDF (165/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Register 54 UTOPHY0
UTOPIA Configuration Register 0 (PHY Side)
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
UTOPHY0 DC_H
Written and Read by CPU
Bit
15
14
13
12
11
10
9
8
unused(4:0)
UTQUEUEOV(6:4)
Bit
7
6
5
4
3
2
1
0
UTQUEUEOV(3:0)
BUS UTPAR UTCONFIG(1:0)
•
UTQUEUEOV
(6:0)
UTOPIA Queue Overflow (downstream transmit)
Bit-field UTQUEUEOV determines the queue overflow level for
each UTOPIA queue.
Note: The shared UTOPIA buffer size is 64 cells.
BUS
The UTOPIA interface can be used with 16-bit or 8-bit bus width:
0
8-bit mode at PHY side.
1
16-bit mode at PHY side.
UTPAR
Enables the parity check at UTOPIA receive upstream interface:
0
Parity check disabled at PHY side
1
Parity check enabled at PHY side
UTCONFIG(1:0)
Configuration of port mode at PHY side UTOPIA interface:
00
4 x 6 port
01
3 x 8 port
10
2 x 12 port
11
Level 1 mode (4 x 1 port)
Data Sheet
6-165
09.99