PXB4330 Datasheet, PDF (107/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Internal Table 4: Scheduler Occupancy Table Transfer Registers SOT0, SOT1
The Scheduler Occupancy Table Transfer Registers are used to access the internal
Scheduler Occupancy Table (SOT) containing 2*48 entries. Table 6-9 shows an
overview of the registers involved.
Table 6-9 Registers for SOT Table Access
31
0
SOT RAM entry
RAM Select:
15
0 15
0
15
0
SOT1
SOT0
MAR=03_H
Entry select:
15
0 15
0
15
0
MASK1
MASK0
WAR (0..47_D,
64_D..111_D)
SOT0 and SOT1 are the transfer registers for one 32-bit SOT table entry. The Scheduler
number representing the table entry which needs to be Read or modified must be written
to the Word Address Register (WAR). The dedicated SOT table entry is Read into the
SOT1/SOT0 Registers or modified by the SOT1/SOT0 register values with a Read-
Modify-Write mechanism. The associated Mask Registers MASK0 and MASK1 allow a
bit-by-bit selection between Read (1) and Write (0) operation. In case of Read operation,
the dedicated SOT1/SOT0 register bit will be overwritten by the respective SOT table
entry bit value. In case of Write operation, the dedicated SOT1/SOT0 register bit will
modify the respective SOT table entry bit value.
The Read-Modify-Write process is controlled by the Memory Address Register (MAR).
The 5 LSBs (= Bit 4..0) of the MAR register select the memory/table that will be
accessed; to select the SOT table, bit field MAR(4:0) must be set to 3. Bit 5 of MAR starts
the transfer and is automatically cleared after execution of the Read-Modify-Write
process.
Data Sheet
6-107
09.99