PXB4330 Datasheet, PDF (192/201 Pages) Infineon Technologies AG – ICs for Communications

7.4.6 Reset Timing
power-on
VDD
CLK
RESET
PXB 4330
Electrical Characteristics
151
150
Figure 7-10 Reset Timing
Table 7-15 Reset Timing
No. Parameter
min.
150 RESET pulse width
120
151 Number of SYSCLK cycles during 2
RESET active
Limit Values
max.
Unit
ns
SYSCLK
cycles
Note: RESET may be asynchronous to CLK when asserted or deasserted. RESET may
be asserted during power-up or asserted after power-up. Nevertheless,
deassertion must be at a clean, bounce-free edge.
Data Sheet
7-192
09.99